Peripheral Component Interconnect — Änderungen 3887 → 3891

Zeile 12: Zeile 12:
 
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=== Aufbau des Konfigurations-Register ===
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=== Aufbau des Konfigurations-Adressraum ===
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{| border="1"
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{| {{Prettytable}} align="right"
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! Register || 31-24       || 23-16         || 15-8         || 7-0
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|- align="center"
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|-
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! Register || width="22%" | 31-24 || width="22%" | 23-16 || width="22%" | 15-8 || width="22%" | 7-0
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| 00       || colspan="2" | Device ID      || colspan="2" | Vendor ID
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|- align="center"
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|-
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| 0x00       || colspan="2" | Device ID      || colspan="2" | Vendor ID
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| 04       || colspan="2" | Status        || colspan="2" | Command
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|- align="center"
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|-
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| 0x04       || colspan="2" | Status        || colspan="2" | Command
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| 08       || Classcode  || Subclass      || colspan="2" | Revision ID
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|- align="center"
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|-
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| 0x08       || colspan="3" | Classcode || Revision ID
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|- align="center"
 
| 0x0C    || BIST        || Header Type  || Latency Timer || Cache Line Size
 
| 0x0C    || BIST        || Header Type  || Latency Timer || Cache Line Size
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|-
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|}
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Die ersten 16&nbsp;Byte sind für alle PCI-Geräte gleich.
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*''Classcode'' ist noch einmal geteilt. Die oberen 8&nbsp;Bit repräsentieren die ''Haput''-Klasse. Die mittleren 8&nbsp;Bit stehen für die Subclass und die unter 8&nbsp;Bit für das ''Programming Interface''.
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*''Header Type'' spezifiziert den Inhalt der Register 0x10-0x3C, wobei Bit&nbsp;7 angibt ob es sich um ein Multifunction-Device handelt oder nicht.
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:{| {{Prettytable}}
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|- align="center"
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! Header Type || Kurze Beschreibung
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|- align="center"
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| 0x00 || [[#Header_Type_0x00|Standard]]
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|- align="center"
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| 0x01 || PCI/PCI-Bridge
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|- align="center"
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| 0x02 || CardBus-Bridge
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|}
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====Header Type 0x00====
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{| {{Prettytable}}
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|- align="center"
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! Register || width="22%" | 31-24 || width="22%" | 23-16 || width="22%" | 15-8 || width="22%" | 7-0
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|- align="center"
 
| 0x10    || colspan="4" | Base Address 0 (BAR0)
 
| 0x10    || colspan="4" | Base Address 0 (BAR0)
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|-
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|- align="center"
 
| 0x14    || colspan="4" | Base Address 1 (BAR1)
 
| 0x14    || colspan="4" | Base Address 1 (BAR1)
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|-
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|- align="center"
 
| 0x18    || colspan="4" | Base Address 2 (BAR2)
 
| 0x18    || colspan="4" | Base Address 2 (BAR2)
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|-
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|- align="center"
 
| 0x1C    || colspan="4" | Base Address 3 (BAR3)
 
| 0x1C    || colspan="4" | Base Address 3 (BAR3)
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|-
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|- align="center"
 
| 0x20    || colspan="4" | Base Address 4 (BAR4)
 
| 0x20    || colspan="4" | Base Address 4 (BAR4)
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|-
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|- align="center"
 
| 0x24    || colspan="4" | Base Address 5 (BAR5)
 
| 0x24    || colspan="4" | Base Address 5 (BAR5)
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|-
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|- align="center"
 
| 0x28    || colspan="4" | Cardbus CIS Pointer
 
| 0x28    || colspan="4" | Cardbus CIS Pointer
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|-
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|- align="center"
 
| 0x2C    || colspan="2" | Subsystem ID || colspan="2" | Subsystem Vendor ID
 
| 0x2C    || colspan="2" | Subsystem ID || colspan="2" | Subsystem Vendor ID
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|-
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|- align="center"
 
| 0x30    || colspan="4" | Expansion ROM base address
 
| 0x30    || colspan="4" | Expansion ROM base address
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|-
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|- align="center"
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| 0x34    || colspan="4" | Reserviert
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| 0x34    || colspan="4" bgcolor="#bbb" | Reserviert
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|-
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|- align="center"
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| 0x38    || colspan="4" | Reserviert
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| 0x38    || colspan="4" bgcolor="#bbb" | Reserviert
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|-
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|- align="center"
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| 0x3C     || Max Latency || Min Grant || Interrupt Pin     || Interrupt Line
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| 0x3C || Max Latency || Min Grant || Interrupt Pin || Interrupt Line
 
|}
 
|}
 
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