Peripheral Component Interconnect — Änderungen 3892 → 3899

Zeile 65: Zeile 65:
 
| 0x30    || colspan="4" | Expansion ROM base address
 
| 0x30    || colspan="4" | Expansion ROM base address
 
|- align="center"
 
|- align="center"
−
| 0x34    || colspan="4" bgcolor="#bbb" | Reserviert
+
| 0x34    || colspan="4" rowspan="2" bgcolor="#bbb" | Reserviert
 
|- align="center"
 
|- align="center"
−
| 0x38     || colspan="4" bgcolor="#bbb" | Reserviert
+
| 0x38
 
|- align="center"
 
|- align="center"
 
| 0x3C || Max Latency || Min Grant || Interrupt Pin || Interrupt Line
 
| 0x3C || Max Latency || Min Grant || Interrupt Pin || Interrupt Line
 
|}
 
|}
 
<br />
 
<br />
 +
 +
====Header Type 0x01====
 +
{| {{Prettytable}}
 +
|- align="center"
 +
! Register || width="22%" | 31-24 || width="22%" | 23-16 || width="22%" | 15-8 || width="22%" | 7-0
 +
|- align="center"
 +
| 0x10 || colspan="4" rowspan="2" bgcolor="#bbb" | Reserviert
 +
|- align="center"
 +
| 0x14
 +
|- align="center"
 +
| 0x18 || Secondary latency timer || Subordinate bus № || Secondary bus № || Primary bus №
 +
|- align="center"
 +
| 0x1C || colspan="2" | Secondary Status || I/O Limit || I/O base
 +
|- align="center"
 +
| 0x20 || colspan="2" |Memory limit || colspan="2" | Memory base
 +
|- align="center"
 +
| 0x24 || colspan="2" | Prefetchable memory limit || colspan="2" | Prefetchable memory base
 +
|- align="center"
 +
| 0x28 || colspan="4" | Prefetchable base upper 32 bits
 +
|- align="center"
 +
| 0x2C || colspan="4" | Prefetchable limit upper 32 bits
 +
|- align="center"
 +
| 0x30 || colspan="2" | I/O limit upper 16 bits || colspan="2" | I/O base upper 16 bits
 +
|- align="center"
 +
| 0x34 || colspan="3" bgcolor="#bbb" | Reserviert || Capabilities pointer
 +
|- align="center"
 +
| 0x38 || colspan="4" bgcolor="#bbb" | Reserviert
 +
|- align="center"
 +
| 0x3C || colspan="2" | Bridge control || Interrupt pin || Interrupt line
 +
|}
  
 
=== Codebeispiel ===
 
=== Codebeispiel ===