Peripheral Component Interconnect — Änderungen 3903 → 3904

Zeile 76: Zeile 76:
 
! Register || width="22%" | 31-24 || width="22%" | 23-16 || width="22%" | 15-8 || width="22%" | 7-0
 
! Register || width="22%" | 31-24 || width="22%" | 23-16 || width="22%" | 15-8 || width="22%" | 7-0
 
|- align="center"
 
|- align="center"
−
| 0x10 || colspan="4" rowspan="2" bgcolor="#bbb" | Reserviert
+
| 0x10 || colspan="4" rowspan="2" | Base address
 
|- align="center"
 
|- align="center"
 
| 0x14
 
| 0x14
Zeile 96: Zeile 96:
 
| 0x34 || colspan="3" bgcolor="#bbb" | Reserviert || Capabilities pointer
 
| 0x34 || colspan="3" bgcolor="#bbb" | Reserviert || Capabilities pointer
 
|- align="center"
 
|- align="center"
−
| 0x38 || colspan="4" bgcolor="#bbb" | Reserviert
+
| 0x38 || colspan="4" | Extension ROM base address
 
|- align="center"
 
|- align="center"
 
| 0x3C || colspan="2" | Bridge control || Interrupt pin || Interrupt line
 
| 0x3C || colspan="2" | Bridge control || Interrupt pin || Interrupt line