Peripheral Component Interconnect — Änderungen 3904 → 3905

Zeile 76: Zeile 76:
 
! Register || width="22%" | 31-24 || width="22%" | 23-16 || width="22%" | 15-8 || width="22%" | 7-0
 
! Register || width="22%" | 31-24 || width="22%" | 23-16 || width="22%" | 15-8 || width="22%" | 7-0
 
|- align="center"
 
|- align="center"
−
| 0x10 || colspan="4" rowspan="2" | Base address
+
| 0x10 || colspan="4" | Base address 0
 
|- align="center"
 
|- align="center"
−
| 0x14
+
| 0x14 || colspan="4" | Base address 1
 
|- align="center"
 
|- align="center"
 
| 0x18 || Secondary latency timer || Subordinate bus № || Secondary bus № || Primary bus №
 
| 0x18 || Secondary latency timer || Subordinate bus № || Secondary bus № || Primary bus №