Peripheral Component Interconnect — Änderungen 7214 → 7215

Zeile 25: Zeile 25:
 
! Register || width="22%" | 31-24 || width="22%" | 23-16 || width="22%" | 15-8 || width="22%" | 7-0
 
! Register || width="22%" | 31-24 || width="22%" | 23-16 || width="22%" | 15-8 || width="22%" | 7-0
 
|- align="center"
 
|- align="center"
−
| 0x00       || colspan="2" | Device ID      || colspan="2" | Vendor ID
+
| 0x000       || colspan="2" | Device ID      || colspan="2" | Vendor ID
 
|- align="center"
 
|- align="center"
−
| 0x04       || colspan="2" | Status        || colspan="2" | Command
+
| 0x004       || colspan="2" | Status        || colspan="2" | Command
 
|- align="center"
 
|- align="center"
−
| 0x08       || colspan="3" | Classcode || Revision ID
+
| 0x008       || colspan="3" | Classcode || Revision ID
 
|- align="center"
 
|- align="center"
−
| 0x0C     || BIST        || Header Type  || Latency Timer || Cache Line Size
+
| 0x00C     || BIST        || Header Type  || Latency Timer || Cache Line Size
 
|- align="center"
 
|- align="center"
−
| 0x10     || colspan="4" bgcolor="#bbb" | Header Type Specific
+
| 0x010     || colspan="4" bgcolor="#bbb" | Header Type Specific
 
|- align="center"
 
|- align="center"
−
| 0x14     || colspan="4" bgcolor="#bbb" | Header Type Specific
+
| 0x014     || colspan="4" bgcolor="#bbb" | Header Type Specific
 
|- align="center"
 
|- align="center"
−
| 0x18     || colspan="4" bgcolor="#bbb" | Header Type Specific
+
| 0x018     || colspan="4" bgcolor="#bbb" | Header Type Specific
 
|- align="center"
 
|- align="center"
−
| 0x1C     || colspan="4" bgcolor="#bbb" | Header Type Specific
+
| 0x01C     || colspan="4" bgcolor="#bbb" | Header Type Specific
 
|- align="center"
 
|- align="center"
−
| 0x20     || colspan="4" bgcolor="#bbb" | Header Type Specific
+
| 0x020     || colspan="4" bgcolor="#bbb" | Header Type Specific
 
|- align="center"
 
|- align="center"
−
| 0x24     || colspan="4" bgcolor="#bbb" | Header Type Specific
+
| 0x024     || colspan="4" bgcolor="#bbb" | Header Type Specific
 
|- align="center"
 
|- align="center"
−
| 0x28     || colspan="4" bgcolor="#bbb" | Header Type Specific
+
| 0x028     || colspan="4" bgcolor="#bbb" | Header Type Specific
 
|- align="center"
 
|- align="center"
−
| 0x2C     || colspan="4" bgcolor="#bbb" | Header Type Specific
+
| 0x02C     || colspan="4" bgcolor="#bbb" | Header Type Specific
 
|- align="center"
 
|- align="center"
−
| 0x30     || colspan="4" bgcolor="#bbb" | Header Type Specific
+
| 0x030     || colspan="4" bgcolor="#bbb" | Header Type Specific
 
|- align="center"
 
|- align="center"
−
| 0x34 || colspan="3" bgcolor="#bbb" | Header Type Specific || Capabilities Pointer
+
| 0x034 || colspan="3" bgcolor="#bbb" | Header Type Specific || Capabilities Pointer
 
|- align="center"
 
|- align="center"
−
| 0x38     || colspan="4" bgcolor="#bbb" | Header Type Specific
+
| 0x038     || colspan="4" bgcolor="#bbb" | Header Type Specific
 
|- align="center"
 
|- align="center"
−
| 0x3C || colspan="2" bgcolor="#bbb" | Header Type Specific || Interrupt Pin || Interrupt Line
+
| 0x03C || colspan="2" bgcolor="#bbb" | Header Type Specific || Interrupt Pin || Interrupt Line
 
|}
 
|}
 
*Die ''Vendor ID''s werden von PCI-SIG verwaltet und den Herstellern zugewiesen. Der Wert 0xffff ist für den Fall reserviert, dass an dieser Stelle kein Gerät vorhanden ist.
 
*Die ''Vendor ID''s werden von PCI-SIG verwaltet und den Herstellern zugewiesen. Der Wert 0xffff ist für den Fall reserviert, dass an dieser Stelle kein Gerät vorhanden ist.
Zeile 84: Zeile 84:
 
! Register || width="22%" | 31-24 || width="22%" | 23-16 || width="22%" | 15-8 || width="22%" | 7-0
 
! Register || width="22%" | 31-24 || width="22%" | 23-16 || width="22%" | 15-8 || width="22%" | 7-0
 
|- align="center"
 
|- align="center"
−
| 0x10     || colspan="4" | Base Address 0 (BAR0)
+
| 0x010     || colspan="4" | Base Address 0 (BAR0)
 
|- align="center"
 
|- align="center"
−
| 0x14     || colspan="4" | Base Address 1 (BAR1)
+
| 0x014     || colspan="4" | Base Address 1 (BAR1)
 
|- align="center"
 
|- align="center"
−
| 0x18     || colspan="4" | Base Address 2 (BAR2)
+
| 0x018     || colspan="4" | Base Address 2 (BAR2)
 
|- align="center"
 
|- align="center"
−
| 0x1C     || colspan="4" | Base Address 3 (BAR3)
+
| 0x01C     || colspan="4" | Base Address 3 (BAR3)
 
|- align="center"
 
|- align="center"
−
| 0x20     || colspan="4" | Base Address 4 (BAR4)
+
| 0x020     || colspan="4" | Base Address 4 (BAR4)
 
|- align="center"
 
|- align="center"
−
| 0x24     || colspan="4" | Base Address 5 (BAR5)
+
| 0x024     || colspan="4" | Base Address 5 (BAR5)
 
|- align="center"
 
|- align="center"
−
| 0x28     || colspan="4" | Cardbus CIS Pointer
+
| 0x028     || colspan="4" | Cardbus CIS Pointer
 
|- align="center"
 
|- align="center"
−
| 0x2C     || colspan="2" | Subsystem ID || colspan="2" | Subsystem Vendor ID
+
| 0x02C     || colspan="2" | Subsystem ID || colspan="2" | Subsystem Vendor ID
 
|- align="center"
 
|- align="center"
−
| 0x30     || colspan="4" | Expansion ROM base address
+
| 0x030     || colspan="4" | Expansion ROM base address
 
|- align="center"
 
|- align="center"
−
| 0x34 || colspan="3" bgcolor="#bbb" | Reserviert || Capabilities Pointer
+
| 0x034 || colspan="3" bgcolor="#bbb" | Reserviert || Capabilities Pointer
 
|- align="center"
 
|- align="center"
−
| 0x38     || colspan="4" bgcolor="#bbb" | Reserviert
+
| 0x038     || colspan="4" bgcolor="#bbb" | Reserviert
 
|- align="center"
 
|- align="center"
−
| 0x3C || Max Latency || Min Grant || Interrupt Pin || Interrupt Line
+
| 0x03C || Max Latency || Min Grant || Interrupt Pin || Interrupt Line
 
|}
 
|}
  
Zeile 114: Zeile 114:
 
! Register || width="22%" | 31-24 || width="22%" | 23-16 || width="22%" | 15-8 || width="22%" | 7-0
 
! Register || width="22%" | 31-24 || width="22%" | 23-16 || width="22%" | 15-8 || width="22%" | 7-0
 
|- align="center"
 
|- align="center"
−
| 0x10 || colspan="4" | Base address 0
+
| 0x010 || colspan="4" | Base address 0
 
|- align="center"
 
|- align="center"
−
| 0x14 || colspan="4" | Base address 1
+
| 0x014 || colspan="4" | Base address 1
 
|- align="center"
 
|- align="center"
−
| 0x18 || Secondary latency timer || Subordinate bus № || Secondary bus № || Primary bus №
+
| 0x018 || Secondary latency timer || Subordinate bus № || Secondary bus № || Primary bus №
 
|- align="center"
 
|- align="center"
−
| 0x1C || colspan="2" | Secondary Status || I/O Limit || I/O base
+
| 0x01C || colspan="2" | Secondary Status || I/O Limit || I/O base
 
|- align="center"
 
|- align="center"
−
| 0x20 || colspan="2" |Memory limit || colspan="2" | Memory base
+
| 0x020 || colspan="2" |Memory limit || colspan="2" | Memory base
 
|- align="center"
 
|- align="center"
−
| 0x24 || colspan="2" | Prefetchable memory limit || colspan="2" | Prefetchable memory base
+
| 0x024 || colspan="2" | Prefetchable memory limit || colspan="2" | Prefetchable memory base
 
|- align="center"
 
|- align="center"
−
| 0x28 || colspan="4" | Prefetchable base upper 32 bits
+
| 0x028 || colspan="4" | Prefetchable base upper 32 bits
 
|- align="center"
 
|- align="center"
−
| 0x2C || colspan="4" | Prefetchable limit upper 32 bits
+
| 0x02C || colspan="4" | Prefetchable limit upper 32 bits
 
|- align="center"
 
|- align="center"
−
| 0x30 || colspan="2" | I/O limit upper 16 bits || colspan="2" | I/O base upper 16 bits
+
| 0x030 || colspan="2" | I/O limit upper 16 bits || colspan="2" | I/O base upper 16 bits
 
|- align="center"
 
|- align="center"
−
| 0x34 || colspan="3" bgcolor="#bbb" | Reserviert || Capabilities pointer
+
| 0x034 || colspan="3" bgcolor="#bbb" | Reserviert || Capabilities pointer
 
|- align="center"
 
|- align="center"
−
| 0x38 || colspan="4" | Extension ROM base address
+
| 0x038 || colspan="4" | Extension ROM base address
 
|- align="center"
 
|- align="center"
−
| 0x3C || colspan="2" | Bridge control || Interrupt pin || Interrupt line
+
| 0x03C || colspan="2" | Bridge control || Interrupt pin || Interrupt line
 
|}
 
|}