Peripheral Component Interconnect — Änderungen 7253 → 7259

Zeile 115: Zeile 115:
 
! Register || width="22%" | 31-24 || width="22%" | 23-16 || width="22%" | 15-8 || width="22%" | 7-0
 
! Register || width="22%" | 31-24 || width="22%" | 23-16 || width="22%" | 15-8 || width="22%" | 7-0
 
|- align="center"
 
|- align="center"
−
| 0x010 || colspan="4" | Base address 0
+
| 0x010 || colspan="4" | Base Address 0 (BAR0)
 
|- align="center"
 
|- align="center"
−
| 0x014 || colspan="4" | Base address 1
+
| 0x014 || colspan="4" | Base Address 1 (BAR1)
 
|- align="center"
 
|- align="center"
 
| 0x018 || Secondary latency timer || Subordinate bus № || Secondary bus № || Primary bus №
 
| 0x018 || Secondary latency timer || Subordinate bus № || Secondary bus № || Primary bus №