| Zeile 518: | Zeile 518: | ||
Bevor man Daten bzw. Befehle ins Datenregister schreiben darf, muss man im MSR testen, ob das DIO-Bit gelöscht und das MRQ-Bit gesetzt ist. Erst dann ist das Datenregister leer und bereit Daten zu empfangen. | Bevor man Daten bzw. Befehle ins Datenregister schreiben darf, muss man im MSR testen, ob das DIO-Bit gelöscht und das MRQ-Bit gesetzt ist. Erst dann ist das Datenregister leer und bereit Daten zu empfangen. | ||
<c> | <c> | ||
| − | #define NO_ERROR | + | #define NO_ERROR 0; |
| − | #define ERROR_TIMEOUT | + | #define ERROR_TIMEOUT 1; |
| − | + | uint8_t error = NO_ERROR; | |
| − | + | void send_cmd(uint8_t cmd) | |
{ | { | ||
send_data(cmd); | send_data(cmd); | ||
} | } | ||
| − | + | void send_data(uint8_t data) | |
{ | { | ||
| − | + | for (uint8_t timeout = 0; timeout < 200; timeout++) | |
| − | for (timeout=0; timeout<200; timeout++) | ||
{ | { | ||
| − | if ( (inb(MSR) & (MSR_MASK_DATAREG|MSR_MASK_DIO2CPU)) == MSR_MASK_DATAREG) | + | if ( (inb(MSR) & (MSR_MASK_DATAREG | MSR_MASK_DIO2CPU)) == MSR_MASK_DATAREG) |
{ | { | ||
| − | outb(CMD,cmd); | + | outb(CMD, cmd); |
error = NO_ERROR; | error = NO_ERROR; | ||
return; | return; | ||
| Zeile 550: | Zeile 549: | ||
<c> | <c> | ||
| − | + | uint8_t read_data() | |
{ | { | ||
| − | + | for(uint8_t timeout = 0; timeout < 200; timeout++) | |
| − | for(timeout=0; timeout<200; timeout++) | ||
{ | { | ||
| − | if( (inb(MSR) & (MSR_MASK_DATAREG|MSR_MASK_DIO2CPU)) == (MSR_MASK_DATAREG|MSR_MASK_DIO2CPU)) | + | if( (inb(MSR) & (MSR_MASK_DATAREG | MSR_MASK_DIO2CPU)) == (MSR_MASK_DATAREG | MSR_MASK_DIO2CPU)) |
{ | { | ||
error = NO_ERROR; | error = NO_ERROR; | ||
| Zeile 569: | Zeile 567: | ||
=== Motor starten/anhalten === | === Motor starten/anhalten === | ||
<c> | <c> | ||
| − | + | void start_motor(uint8_t n) | |
{ | { | ||
if (!drive_states[n].motor_on) | if (!drive_states[n].motor_on) | ||
{ | { | ||
| − | outb(DOR,n | (0x01<<(n+4)) | DOR_MASK_NRESET | DOR_MASK_DMA); | + | outb(DOR, n | (0x01<<(n+4)) | DOR_MASK_NRESET | DOR_MASK_DMA); |
} | } | ||
} | } | ||
| − | + | void stop_motor(uint8_t n) | |
{ | { | ||
if (drive_states[n].motor_on) | if (drive_states[n].motor_on) | ||
{ | { | ||
| − | outb(DOR,n | DOR_MASK_NRESET | DOR_MASK_DMA); | + | outb(DOR, n | DOR_MASK_NRESET | DOR_MASK_DMA); |
} | } | ||
} | } | ||
| Zeile 588: | Zeile 586: | ||
=== Laufwerk kallibrieren === | === Laufwerk kallibrieren === | ||
<c> | <c> | ||
| − | + | void calibrate_drive(uint8_t drive) | |
{ | { | ||
...TODO | ...TODO | ||
| Zeile 595: | Zeile 593: | ||
=== Schreib-/Lesekopf postionieren === | === Schreib-/Lesekopf postionieren === | ||
<c> | <c> | ||
| − | + | bool seek_head(uint8_t cyl, uint8_t head, uint8_t sector) | |
{ | { | ||
...TODO | ...TODO | ||
| Zeile 602: | Zeile 600: | ||
=== Reset === | === Reset === | ||
<c> | <c> | ||
| − | + | void reset() | |
{ | { | ||
| − | |||
| − | |||
outb(DOR, 0); | outb(DOR, 0); | ||
sleep(10); | sleep(10); | ||
outb(DOR, DOR_MASK_NRESET | DOR_MASK_DMA); | outb(DOR, DOR_MASK_NRESET | DOR_MASK_DMA); | ||
wait_irq(); | wait_irq(); | ||
| − | for(i=0; i<4; i++) | + | for(int i = 0; i < 4; i++) |
{ | { | ||
check_interrupt_status(); | check_interrupt_status(); | ||
| Zeile 626: | Zeile 622: | ||
#define CMD_READ_SECTOR (0x06 | 0x40) | #define CMD_READ_SECTOR (0x06 | 0x40) | ||
| − | + | bool transfer_sector(uint8_t drive, uint8_t cylinder, uint8_t head, uint8_t sector, bool write, void* buffer) | |
{ | { | ||
| − | |||
select_drive(drive); //TODO | select_drive(drive); //TODO | ||
start_motor(drive); //TODO | start_motor(drive); //TODO | ||
| Zeile 634: | Zeile 629: | ||
dma_begin_transfer(buffer, write); | dma_begin_transfer(buffer, write); | ||
| − | for (i=0; i<5; i++) | + | for (int i = 0; i<5; i++) |
{ | { | ||
send_command(wrie ? CMD_WRIE_SECTOR : CMD_READ_SECTOR); | send_command(wrie ? CMD_WRIE_SECTOR : CMD_READ_SECTOR); | ||
| − | send_data(drive | head<<2 | + | send_data(drive | head<<2); |
send_data(cylinder); | send_data(cylinder); | ||
send_data(head); | send_data(head); | ||
| Zeile 656: | Zeile 651: | ||
{ | { | ||
check_interrupt_status(); | check_interrupt_status(); | ||
| − | return | + | return true; |
} | } | ||
} | } | ||
/* fünf Fehlversuche */ | /* fünf Fehlversuche */ | ||
| − | return | + | return false; |
} | } | ||
</c> | </c> | ||