'''Peripheral Component Interconnect''' (kurz '''PCI''') ist ein [[:Kategorie:Bus | Bus]] zur leichten Verbindung von Peripheriegeräten mit der CPU.

== Konfigurations-Register ==
Jedes PCI-Gerät besitzt ein Konfigurations-Register, welches 256 Byte groß ist. Gelesen und beschrieben wird es 32bit-weise mithilfe eines Adress-I/O-Ports (0xCF8) und eines Daten-I/O-Ports (0xCFC).

=== Aufbau des Adress-I/O-Ports ===
{| {{Prettytable}}
|- align="center"
! 31         || 30-24      || 23-16     || 15-11        || 10-8            || 7-0
|- align="center"
| Enable Bit || bgcolor="#bbb" | Reserviert || Busnummer || Gerätenummer || Funktionsnummer || Registernummer
|}
<br />

=== Aufbau des Konfigurations-Adressraum ===
{| {{Prettytable}} align="right"
|- align="center"
! Register || width="22%" | 31-24 || width="22%" | 23-16 || width="22%" | 15-8 || width="22%" | 7-0
|- align="center"
| 0x00       || colspan="2" | Device ID      || colspan="2" | Vendor ID
|- align="center"
| 0x04       || colspan="2" | Status         || colspan="2" | Command
|- align="center"
| 0x08       || colspan="3" | Classcode || Revision ID
|- align="center"
| 0x0C     || BIST        || Header Type   || Latency Timer || Cache Line Size
|}
Die ersten 16&nbsp;Byte sind für alle PCI-Geräte gleich.

*''Classcode'' ist noch einmal geteilt. Die oberen 8&nbsp;Bit repräsentieren die ''Base Class''. Die mittleren 8&nbsp;Bit stehen für die ''Subclass'' und die unter 8&nbsp;Bit für das ''Programming Interface''.
*''Header Type'' spezifiziert den Inhalt der Register 0x10-0x3C, wobei Bit&nbsp;7 angibt ob es sich um ein Multifunction-Device handelt oder nicht.
:{| {{Prettytable}}
|- align="center"
! Header Type || Kurze Beschreibung
|- align="center"
| 0x00 || [[#Header_Type_0x00|Standard]]
|- align="center"
| 0x01 || [[#Header_Type_0x01|PCI/PCI-Bridge]]
|- align="center"
| 0x02 || CardBus-Bridge
|}

====Header Type 0x00====
{| {{Prettytable}}
|- align="center"
! Register || width="22%" | 31-24 || width="22%" | 23-16 || width="22%" | 15-8 || width="22%" | 7-0
|- align="center"
| 0x10     || colspan="4" | Base Address 0 (BAR0)
|- align="center"
| 0x14     || colspan="4" | Base Address 1 (BAR1)
|- align="center"
| 0x18     || colspan="4" | Base Address 2 (BAR2)
|- align="center"
| 0x1C     || colspan="4" | Base Address 3 (BAR3)
|- align="center"
| 0x20     || colspan="4" | Base Address 4 (BAR4)
|- align="center"
| 0x24     || colspan="4" | Base Address 5 (BAR5)
|- align="center"
| 0x28     || colspan="4" | Cardbus CIS Pointer
|- align="center"
| 0x2C     || colspan="2" | Subsystem ID || colspan="2" | Subsystem Vendor ID
|- align="center"
| 0x30     || colspan="4" | Expansion ROM base address
|- align="center"
| 0x34     || colspan="4" rowspan="2" bgcolor="#bbb" | Reserviert
|- align="center"
| 0x38
|- align="center"
| 0x3C || Max Latency || Min Grant || Interrupt Pin || Interrupt Line
|}

====Header Type 0x01====
{| {{Prettytable}}
|- align="center"
! Register || width="22%" | 31-24 || width="22%" | 23-16 || width="22%" | 15-8 || width="22%" | 7-0
|- align="center"
| 0x10 || colspan="4" | Base address 0
|- align="center"
| 0x14 || colspan="4" | Base address 1
|- align="center"
| 0x18 || Secondary latency timer || Subordinate bus № || Secondary bus № || Primary bus №
|- align="center"
| 0x1C || colspan="2" | Secondary Status || I/O Limit || I/O base
|- align="center"
| 0x20 || colspan="2" |Memory limit || colspan="2" | Memory base
|- align="center"
| 0x24 || colspan="2" | Prefetchable memory limit || colspan="2" | Prefetchable memory base
|- align="center"
| 0x28 || colspan="4" | Prefetchable base upper 32 bits
|- align="center"
| 0x2C || colspan="4" | Prefetchable limit upper 32 bits
|- align="center"
| 0x30 || colspan="2" | I/O limit upper 16 bits || colspan="2" | I/O base upper 16 bits
|- align="center"
| 0x34 || colspan="3" bgcolor="#bbb" | Reserviert || Capabilities pointer
|- align="center"
| 0x38 || colspan="4" | Extension ROM base address
|- align="center"
| 0x3C || colspan="2" | Bridge control || Interrupt pin || Interrupt line
|}

=== Codebeispiel ===
<c>
#define PCI_CONFIG_DATA    0xCFC
#define PCI_CONFIG_ADDRESS 0xCF8

/**
 * Liest ein Dword aus einem PCI-Konfigurations-Register
 *  @param bus Bus
 *  @param dev Gerät
 *  @param func Funktion
 *  @param offset Registernummer
 *  @return Register content
 */
int pci_config_readd(int bus,int dev,int func,int offset) {
  int val;
  int address = 0x80000000|(bus<<16)|(dev<<11)|(func<<8)|(offset&0xFC);
  outl(PCI_CONFIG_ADDRESS,address);
  val = inl(PCI_CONFIG_DATA);
  return val;
}

/**
 * Schreibt ein Dword in in ein PCI-Konfigurations-Register
 *  @param bus Bus
 *  @param dev Gerät
 *  @param func Funktion
 *  @param offset Registernummer
 *  @param val Wert zum Schreiben
 */
void pci_config_writed(int bus,int dev,int func,int offset,int val) {
  int address = 0x80000000|(bus<<16)|(dev<<11)|(func<<8)|(offset&0xFC);
  outl(PCI_CONFIG_ADDRESS,address);
  outl(PCI_CONFIG_DATA,val);
}
</c>

== Classcodes ==
{| {{Prettytable}}
! Class     || Beschreibung
|-
| 0x00      || [[#Class_0x00_-_Pre_2.0 | Alle Geräte die gebaut wurden bevor Classcodes eingeführt wurden ]]
|-
| 0x01      || [[#Class_0x01_-_Massenspeicher | Massenspeicher]]
|-
| 0x02      || [[#Class_0x02_-_Netzwerk-Controller | Netzwerk-Controller]]
|-
| 0x03      || [[#Class_0x03_-_Bildschirm-Controller | Bildschirm-Controller]]
|-
| 0x04      || [[#Class_0x04_-_Multimedia-Geräte | Multimedia-Geräte]]
|-
| 0x05      || [[#Class_0x05_-_Speicher-Controller | Speicher-Controller]]
|-
| 0x06      || [[#Class_0x06_-_Bridge-Geräte | Bridge-Geräte]]
|-
| 0x07      || [[#Class_0x07_-_Controller zur einfachen Kommunikation | Controller zur einfachen Kommunikation]]
|-
| 0x08      || [[#Class_0x08_-_System-Peripherie | System-Peripherie]]
|-
| 0x09      || [[#Class_0x09_-_Input-Geräte | Input-Geräte]]
|-
| 0x0A      || [[#Class_0x0A_-_Docking-Stationen | Docking-Stationen]]
|-
| 0x0B      || [[#Class_0x0B_-_Prozessoren | Prozessoren]]
|-
| 0x0C      || [[#Class_0x0C_-_Seriell-Bus-Controller | Seriell-Bus-Controller]]
|-
| 0x0D      || [[#Class_0x0D_-_Wireless-Controller | Wireless-Controller]]
|- bgcolor='#BBB'
| 0x0E-0xFE || ''Reserviert''
|-
| 0xFF      || Sonstige
|}
<br />

=== Class 0x00 - Pre 2.0 ===
{| {{Prettytable}}
! Subclass || Beschreibung
|-
| 0x00     || Alle nicht-VGA-Geräte
|-
| 0x01     || VGA-Geräte
|}
<br />

=== Class 0x01 - Massenspeicher ===
{| {{Prettytable}}
! Subclass || Beschreibung
|-
| 0x00     || SCSI
|-
| 0x01     || IDE
|-
| 0x02     || Floppy
|-
| 0x03     || IPI
|-
| 0x04     || RAID
|-
| 0x05     || ATA Controller (mit DMA)
|-
| 0x80     || Anderer Massenspeicher
|}
<br />

=== Class 0x02 - Netzwerk-Controller ===
{| {{Prettytable}}
! Subclass || Beschreibung
|-
| 0x00     || Ethernet
|-
| 0x01     || Token Ring
|-
| 0x02     || FDDI
|-
| 0x03     || ATM
|-
| 0x80     || Anderer Netzwerk-Controller
|}
<br />

=== Class 0x03 - Bildschirm-Controller ===
{| {{Prettytable}}
! Subclass || Beschreibung
|-
| 0x00     || VGA-Kompatibel
|-
| 0x01     || XGA
|-
| 0x80     || Anderer Bildschirm-Controller
|}
<br />

=== Class 0x04 - Multimedia-Geräte ===
{| {{Prettytable}}
! Subclass || Beschreibung
|-
| 0x00     || Video-Gerät
|-
| 0x01     || Audio-Gerät
|-
| 0x80     || Anderes Multimedia-Gerät
|}
<br />

=== Class 0x05 - Speicher-Controller ===
{| {{Prettytable}}
! Subclass || Beschreibung
|-
| 0x00     || RAM
|-
| 0x01     || Flash-Speicher
|-
| 0x80     || Anderer Speicher
|}
<br />

=== Class 0x06 - Bridge-Geräte ===
{| {{Prettytable}}
! Subclass || Beschreibung
|-
| 0x00     || Host/PCI-Bridge
|-
| 0x01     || PCI/ISA-Bridge
|-
| 0x02     || PCI/EISA-Bridge
|-
| 0x03     || PCI/MicroChannel-Bridge
|-
| 0x04     || PCI/PCI-Bridge
|-
| 0x05     || PCI/PCMCIA-Bridge
|-
| 0x06     || PCI/NuBus-Bridge
|-
| 0x07     || PCI/CardBus-Bridge
|-
| 0x09     || Semitransparente PCI/PCI-Bridge
|-
| 0x0A     || InfiniBand/PCI-Brige
|-
| 0x80     || Anderer Bridge-Typ
|}
<br />

=== Class 0x07 - Controller zur einfachen Kommunikation ===
{| {{Prettytable}}
! Subclass || Beschreibung
|-
| 0x00     || Serielle Schnittstelle
|-
| 0x01     || Parallelport
|-
| 0x04     || GPIB (IEEE488.1/2) Controller
|-
| 0x05     || SmartCard
|-
| 0x80     || Andere
|}
<br />

=== Class 0x08 - System-Peripherie ===
{| {{Prettytable}}
! Subclass || Beschreibung
|-
| 0x00     || [[Programmable Interrupt Controller]]
|-
| 0x01     || [[Direct Memory Access]]
|-
| 0x02     || Timer
|-
| 0x03     || [[Realtime Clock]]
|-
| 0x80     || Andere System-Peripherie
|}
<br />

=== Class 0x09 - Input-Geräte ===
{| {{Prettytable}}
! Subclass || Beschreibung
|-
| 0x00     || Tastatur
|-
| 0x01     || Digitizer (Stift)
|-
| 0x02     || Maus
|-
| 0x80     || Anderes Input-Gerät
|}
<br />

=== Class 0x0A - Docking-Stationen ===
{| {{Prettytable}}
! Subclass || Beschreibung
|-
| 0x00     || Normale Docking-Station
|-
| 0x80     || Andere Docking-Station
|}
<br />

=== Class 0x0B - Processors ===
{| {{Prettytable}}
! Subclass || Beschreibung
|-
| 0x00     || 386
|-
| 0x01     || 486
|-
| 0x02     || Pentium
|-
| 0x10     || Alpha
|-
| 0x20     || PowerPC
|-
| 0x40     || Co-Processor
|-
|}
<br />

=== Class 0x0C - Seriell-Bus-Controller ===
{| {{Prettytable}}
! Subclass || Beschreibung
|-
| 0x00     || Firewire (IEEE 1394)
|-
| 0x01     || ACCESS-Bus
|-
| 0x02     || SSA (Serial Storage Architecture)
|-
| 0x03     || [[USB]] (Universal Serial Bus)
|}
<br />

=== Class 0x0D - Wireless-Controller ===
{| {{Prettytable}}
! Subclass || Beschreibung
|-
| 0x11     || Bluetooth
|-
| 0x12     || Broadband
|}
<br />

== Weblinks ==
* [http://pci-ids.ucw.cz/ Linux PCI ID Repositorium] - Enthält viele VendorIDs und die dazugehörigen DeviceIDs

[[Kategorie:Hardware]]
[[Kategorie:Bus]]