==x86 CPU Register==

{| {{Prettytable}}
! Bits  || Register
|-
| 8 || AL, BL, CL, DL, AH, BH, CH, DH
|-
| 16 || AX, BX, CX, DX, DI, SI, BP, SP, CS, DS, ES, FS, GS, SS
|-
| 32 || EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP, EIP, EFLAGS
|-
| 80 || 
|-
| 128 || XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7
|}

==x86-64 CPU Register==
===Allzweckregister===
{|
|
{| {{Prettytable}}
! width="30pt" | 7
! width="30pt" | 6
! width="30pt" | 5
! width="30pt" | 4
! width="30pt" | 3
! width="30pt" | 2
! width="30pt" | 1
! width="30pt" | 0
|-
| colspan="8" align="center" | RAX
|- 
| colspan="4" style="background:lightgrey" |  
| colspan="4" align="center" | EAX
|-
| colspan="6" style="background:lightgrey" | 
| colspan="2" align="center" | AX
|-
| colspan="6" style="background:lightgrey" | 
| align="center" | AH 
| align="center" | AL
|}

|
{| {{Prettytable}}
! width="30pt" | 7
! width="30pt" | 6
! width="30pt" | 5
! width="30pt" | 4
! width="30pt" | 3
! width="30pt" | 2
! width="30pt" | 1
! width="30pt" | 0
|-
| colspan="8" align="center" | RBX
|- 
| colspan="4" style="background:lightgrey" |  
| colspan="4" align="center" | EBX
|-
| colspan="6" style="background:lightgrey" | 
| colspan="2" align="center" | BX
|-
| colspan="6" style="background:lightgrey" | 
| align="center" | BH 
| align="center" | BL
|}

|
{| {{Prettytable}}
! width="30pt" | 7
! width="30pt" | 6
! width="30pt" | 5
! width="30pt" | 4
! width="30pt" | 3
! width="30pt" | 2
! width="30pt" | 1
! width="30pt" | 0
|-
| colspan="8" align="center" | RCX
|- 
| colspan="4" style="background:lightgrey" |  
| colspan="4" align="center" | ECX
|-
| colspan="6" style="background:lightgrey" | 
| colspan="2" align="center" | CX
|-
| colspan="6" style="background:lightgrey" | 
| align="center" | CH 
| align="center" | CL
|}

|-
|
{| {{Prettytable}}
! width="30pt" | 7
! width="30pt" | 6
! width="30pt" | 5
! width="30pt" | 4
! width="30pt" | 3
! width="30pt" | 2
! width="30pt" | 1
! width="30pt" | 0
|-
| colspan="8" align="center" | RDX
|- 
| colspan="4" style="background:lightgrey" |  
| colspan="4" align="center" | EDX
|-
| colspan="6" style="background:lightgrey" | 
| colspan="2" align="center" | DX
|-
| colspan="6" style="background:lightgrey" | 
| align="center" | DH 
| align="center" | DL
|}

|
{| {{Prettytable}}
! width="30pt" | 7
! width="30pt" | 6
! width="30pt" | 5
! width="30pt" | 4
! width="30pt" | 3
! width="30pt" | 2
! width="30pt" | 1
! width="30pt" | 0
|-
| colspan="8" align="center" | R8
|- 
| colspan="4" style="background:lightgrey" |  
| colspan="4" align="center" | R8D
|-
| colspan="6" style="background:lightgrey" | 
| colspan="2" align="center" | R8W
|-
| colspan="7" style="background:lightgrey" |
| align="center" | R8L
|}

|
{| {{Prettytable}}
! width="30pt" | 7
! width="30pt" | 6
! width="30pt" | 5
! width="30pt" | 4
! width="30pt" | 3
! width="30pt" | 2
! width="30pt" | 1
! width="30pt" | 0
|-
| colspan="8" align="center" | R9
|- 
| colspan="4" style="background:lightgrey" |  
| colspan="4" align="center" | R9D
|-
| colspan="6" style="background:lightgrey" | 
| colspan="2" align="center" | R9W
|-
| colspan="7" style="background:lightgrey" |
| align="center" | R9L
|}

|-
|
{| {{Prettytable}}
! width="30pt" | 7
! width="30pt" | 6
! width="30pt" | 5
! width="30pt" | 4
! width="30pt" | 3
! width="30pt" | 2
! width="30pt" | 1
! width="30pt" | 0
|-
| colspan="8" align="center" | R10
|- 
| colspan="4" style="background:lightgrey" |  
| colspan="4" align="center" | R10D
|-
| colspan="6" style="background:lightgrey" | 
| colspan="2" align="center" | R10W
|-
| colspan="7" style="background:lightgrey" |
| align="center" | R10L
|}

|
{| {{Prettytable}}
! width="30pt" | 7
! width="30pt" | 6
! width="30pt" | 5
! width="30pt" | 4
! width="30pt" | 3
! width="30pt" | 2
! width="30pt" | 1
! width="30pt" | 0
|-
| colspan="8" align="center" | R11
|- 
| colspan="4" style="background:lightgrey" |  
| colspan="4" align="center" | R11D
|-
| colspan="6" style="background:lightgrey" | 
| colspan="2" align="center" | R11W
|-
| colspan="7" style="background:lightgrey" |
| align="center" | R11L
|}

|
{| {{Prettytable}}
! width="30pt" | 7
! width="30pt" | 6
! width="30pt" | 5
! width="30pt" | 4
! width="30pt" | 3
! width="30pt" | 2
! width="30pt" | 1
! width="30pt" | 0
|-
| colspan="8" align="center" | R12
|- 
| colspan="4" style="background:lightgrey" |  
| colspan="4" align="center" | R12D
|-
| colspan="6" style="background:lightgrey" | 
| colspan="2" align="center" | R12W
|-
| colspan="7" style="background:lightgrey" |
| align="center" | R12L
|}

|-
|
{| {{Prettytable}}
! width="30pt" | 7
! width="30pt" | 6
! width="30pt" | 5
! width="30pt" | 4
! width="30pt" | 3
! width="30pt" | 2
! width="30pt" | 1
! width="30pt" | 0
|-
| colspan="8" align="center" | R13
|- 
| colspan="4" style="background:lightgrey" |  
| colspan="4" align="center" | R13D
|-
| colspan="6" style="background:lightgrey" | 
| colspan="2" align="center" | R13W
|-
| colspan="7" style="background:lightgrey" |
| align="center" | R13L
|}

|
{| {{Prettytable}}
! width="30pt" | 7
! width="30pt" | 6
! width="30pt" | 5
! width="30pt" | 4
! width="30pt" | 3
! width="30pt" | 2
! width="30pt" | 1
! width="30pt" | 0
|-
| colspan="8" align="center" | R14
|- 
| colspan="4" style="background:lightgrey" |  
| colspan="4" align="center" | R14D
|-
| colspan="6" style="background:lightgrey" | 
| colspan="2" align="center" | R14W
|-
| colspan="7" style="background:lightgrey" |
| align="center" | R14L
|}

|
{| {{Prettytable}}
! width="30pt" | 7
! width="30pt" | 6
! width="30pt" | 5
! width="30pt" | 4
! width="30pt" | 3
! width="30pt" | 2
! width="30pt" | 1
! width="30pt" | 0
|-
| colspan="8" align="center" | R15
|- 
| colspan="4" style="background:lightgrey" |  
| colspan="4" align="center" | R15D
|-
| colspan="6" style="background:lightgrey" | 
| colspan="2" align="center" | R15W
|-
| colspan="7" style="background:lightgrey" |
| align="center" | R15L
|}
|}

===Indexregister===

{|
|
{| {{Prettytable}}
! width="30pt" | 7
! width="30pt" | 6
! width="30pt" | 5
! width="30pt" | 4
! width="30pt" | 3
! width="30pt" | 2
! width="30pt" | 1
! width="30pt" | 0
|-
| colspan="8" align="center" | RDI
|- 
| colspan="4" style="background:lightgrey" |  
| colspan="4" align="center" | EDI
|-
| colspan="6" style="background:lightgrey" | 
| colspan="2" align="center" | DI
|-
| colspan="7" style="background:lightgrey" |
| align="center" | DIL
|}

|
{| {{Prettytable}}
! width="30pt" | 7
! width="30pt" | 6
! width="30pt" | 5
! width="30pt" | 4
! width="30pt" | 3
! width="30pt" | 2
! width="30pt" | 1
! width="30pt" | 0
|-
| colspan="8" align="center" | RSI
|- 
| colspan="4" style="background:lightgrey" |  
| colspan="4" align="center" | ESI
|-
| colspan="6" style="background:lightgrey" | 
| colspan="2" align="center" | SI
|-
| colspan="7" style="background:lightgrey" |
| align="center" | SIL
|}

|}
===Zeigerregister===
{|
|
{| {{Prettytable}}
! width="30pt" | 7
! width="30pt" | 6
! width="30pt" | 5
! width="30pt" | 4
! width="30pt" | 3
! width="30pt" | 2
! width="30pt" | 1
! width="30pt" | 0
|-
| colspan="8" align="center" | RBP
|- 
| colspan="4" style="background:lightgrey" |  
| colspan="4" align="center" | EBP
|-
| colspan="6" style="background:lightgrey" | 
| colspan="2" align="center" | BP
|-
| colspan="7" style="background:lightgrey" |
| align="center" | BPL
|}

|
{| {{Prettytable}}
! width="30pt" | 7
! width="30pt" | 6
! width="30pt" | 5
! width="30pt" | 4
! width="30pt" | 3
! width="30pt" | 2
! width="30pt" | 1
! width="30pt" | 0
|-
| colspan="8" align="center" | RSP
|- 
| colspan="4" style="background:lightgrey" |  
| colspan="4" align="center" | ESP
|-
| colspan="6" style="background:lightgrey" | 
| colspan="2" align="center" | SP
|-
| colspan="7" style="background:lightgrey" |
| align="center" | SPL
|}

|}


{| {{Prettytable}}
! Bits  || Register
|-
| 8 || AL, BL, CL, DL, DIL, SIL, BPL, SPL, R8L, R9L, R10L, R11L, R12L, R13L, R14L, R15L
|-
| 16 || AX, BX, CX, DX, DI, SI, BP, SP, CS, DS, ES, FS, GS, SS, R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W
|-
| 32 || EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP, EIP, EFLAGS, R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D
|-
| 64 || RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, RIP, RFLAGS, R8, R9, R10, R11, R12, R13, R14, R15
|-
| 128 || XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15
|}

{| {{Prettytable}}
| 4
|-
| 2 || || 2
|-
| 1 || 1 || ||
|}