Register — Änderungen 4600 → 4602

Zeile 1: Zeile 1:
 
==x86 CPU Register==
 
==x86 CPU Register==
 +
 
{| {{Prettytable}}
 
{| {{Prettytable}}
 
! Bits  || Register
 
! Bits  || Register
Zeile 8: Zeile 9:
 
|-
 
|-
 
| 32 || EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP, EIP, EFLAGS
 
| 32 || EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP, EIP, EFLAGS
 +
|-
 +
| 80 ||
 
|-
 
|-
 
| 128 || XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7
 
| 128 || XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7
Zeile 13: Zeile 16:
  
 
==x86-64 CPU Register==
 
==x86-64 CPU Register==
 +
===Allzweckregister===
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{| {{Prettytable}}
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! width="30pt" | 7
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! width="30pt" | 6
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! width="30pt" | 5
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! width="30pt" | 4
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! width="30pt" | 3
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! width="30pt" | 2
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! width="30pt" | 1
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! width="30pt" | 0
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|-
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| colspan="8" align="center" | RAX
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|-
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| colspan="4" style="background:lightgrey" | 
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| colspan="4" align="center" | EAX
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|-
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| colspan="6" style="background:lightgrey" |
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| colspan="2" align="center" | AX
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|-
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| colspan="6" style="background:lightgrey" |
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| align="center" | AH
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| align="center" | AL
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|}
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{| {{Prettytable}}
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! width="30pt" | 7
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! width="30pt" | 6
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! width="30pt" | 5
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! width="30pt" | 4
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! width="30pt" | 3
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! width="30pt" | 2
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! width="30pt" | 1
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! width="30pt" | 0
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|-
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| colspan="8" align="center" | RBX
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|-
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| colspan="4" style="background:lightgrey" | 
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| colspan="4" align="center" | EBX
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|-
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| colspan="6" style="background:lightgrey" |
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| colspan="2" align="center" | BX
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|-
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| colspan="6" style="background:lightgrey" |
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| align="center" | BH
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| align="center" | BL
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|}
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{| {{Prettytable}}
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! width="30pt" | 7
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! width="30pt" | 6
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! width="30pt" | 5
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! width="30pt" | 4
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! width="30pt" | 3
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! width="30pt" | 2
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! width="30pt" | 1
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! width="30pt" | 0
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|-
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| colspan="8" align="center" | RCX
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|-
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| colspan="4" style="background:lightgrey" | 
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| colspan="4" align="center" | ECX
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|-
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| colspan="6" style="background:lightgrey" |
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| colspan="2" align="center" | CX
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|-
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| colspan="6" style="background:lightgrey" |
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| align="center" | CH
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| align="center" | CL
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|}
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{| {{Prettytable}}
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! width="30pt" | 7
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! width="30pt" | 6
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! width="30pt" | 5
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! width="30pt" | 4
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! width="30pt" | 3
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! width="30pt" | 2
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! width="30pt" | 1
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! width="30pt" | 0
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|-
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| colspan="8" align="center" | RDX
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|-
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| colspan="4" style="background:lightgrey" | 
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| colspan="4" align="center" | EDX
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|-
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| colspan="6" style="background:lightgrey" |
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| colspan="2" align="center" | DX
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|-
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| colspan="6" style="background:lightgrey" |
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| align="center" | DH
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| align="center" | DL
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|}
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{| {{Prettytable}}
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! width="30pt" | 7
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! width="30pt" | 6
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! width="30pt" | 5
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! width="30pt" | 4
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! width="30pt" | 3
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! width="30pt" | 2
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! width="30pt" | 1
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! width="30pt" | 0
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|-
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| colspan="8" align="center" | R8
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|-
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| colspan="4" style="background:lightgrey" | 
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| colspan="4" align="center" | R8D
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|-
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| colspan="6" style="background:lightgrey" |
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| colspan="2" align="center" | R8W
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|-
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| colspan="7" style="background:lightgrey" |
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| align="center" | R8L
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|}
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{| {{Prettytable}}
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! width="30pt" | 7
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! width="30pt" | 6
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! width="30pt" | 5
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! width="30pt" | 4
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! width="30pt" | 3
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! width="30pt" | 2
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! width="30pt" | 1
 +
! width="30pt" | 0
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|-
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| colspan="8" align="center" | R9
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|-
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| colspan="4" style="background:lightgrey" | 
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| colspan="4" align="center" | R9D
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|-
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| colspan="6" style="background:lightgrey" |
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| colspan="2" align="center" | R9W
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|-
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| colspan="7" style="background:lightgrey" |
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| align="center" | R9L
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|}
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{| {{Prettytable}}
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! width="30pt" | 7
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! width="30pt" | 6
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! width="30pt" | 5
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! width="30pt" | 4
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! width="30pt" | 3
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! width="30pt" | 2
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! width="30pt" | 1
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! width="30pt" | 0
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|-
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| colspan="8" align="center" | R10
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|-
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| colspan="4" style="background:lightgrey" | 
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| colspan="4" align="center" | R10D
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|-
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| colspan="6" style="background:lightgrey" |
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| colspan="2" align="center" | R10W
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|-
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| colspan="7" style="background:lightgrey" |
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| align="center" | R10L
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|}
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{| {{Prettytable}}
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! width="30pt" | 7
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! width="30pt" | 6
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! width="30pt" | 5
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! width="30pt" | 4
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! width="30pt" | 3
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! width="30pt" | 2
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! width="30pt" | 1
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! width="30pt" | 0
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|-
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| colspan="8" align="center" | R11
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|-
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| colspan="4" style="background:lightgrey" | 
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| colspan="4" align="center" | R11D
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|-
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| colspan="6" style="background:lightgrey" |
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| colspan="2" align="center" | R11W
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|-
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| colspan="7" style="background:lightgrey" |
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| align="center" | R11L
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|}
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{| {{Prettytable}}
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! width="30pt" | 7
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! width="30pt" | 6
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! width="30pt" | 5
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! width="30pt" | 4
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! width="30pt" | 3
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! width="30pt" | 2
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! width="30pt" | 1
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! width="30pt" | 0
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|-
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| colspan="8" align="center" | R12
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|-
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| colspan="4" style="background:lightgrey" | 
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| colspan="4" align="center" | R12D
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|-
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| colspan="6" style="background:lightgrey" |
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| colspan="2" align="center" | R12W
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|-
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| colspan="7" style="background:lightgrey" |
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| align="center" | R12L
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|}
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{| {{Prettytable}}
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! width="30pt" | 7
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! width="30pt" | 6
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! width="30pt" | 5
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! width="30pt" | 4
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! width="30pt" | 3
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! width="30pt" | 2
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! width="30pt" | 1
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! width="30pt" | 0
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|-
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| colspan="8" align="center" | R13
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|-
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| colspan="4" style="background:lightgrey" | 
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| colspan="4" align="center" | R13D
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|-
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| colspan="6" style="background:lightgrey" |
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| colspan="2" align="center" | R13W
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|-
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| colspan="7" style="background:lightgrey" |
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| align="center" | R13L
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|}
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{| {{Prettytable}}
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! width="30pt" | 7
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! width="30pt" | 6
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! width="30pt" | 5
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! width="30pt" | 4
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! width="30pt" | 3
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! width="30pt" | 2
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! width="30pt" | 1
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! width="30pt" | 0
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|-
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| colspan="8" align="center" | R14
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|-
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| colspan="4" style="background:lightgrey" | 
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| colspan="4" align="center" | R14D
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|-
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| colspan="6" style="background:lightgrey" |
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| colspan="2" align="center" | R14W
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|-
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| colspan="7" style="background:lightgrey" |
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| align="center" | R14L
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|}
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{| {{Prettytable}}
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! width="30pt" | 7
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! width="30pt" | 6
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! width="30pt" | 5
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! width="30pt" | 4
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! width="30pt" | 3
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! width="30pt" | 2
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! width="30pt" | 1
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! width="30pt" | 0
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|-
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| colspan="8" align="center" | R15
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|-
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| colspan="4" style="background:lightgrey" | 
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| colspan="4" align="center" | R15D
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|-
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| colspan="6" style="background:lightgrey" |
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| colspan="2" align="center" | R15W
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|-
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| colspan="7" style="background:lightgrey" |
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| align="center" | R15L
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|}
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===Indexregister===
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 +
{| {{Prettytable}}
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! width="30pt" | 7
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! width="30pt" | 6
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! width="30pt" | 5
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! width="30pt" | 4
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! width="30pt" | 3
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! width="30pt" | 2
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! width="30pt" | 1
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! width="30pt" | 0
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|-
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| colspan="8" align="center" | RDI
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|-
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| colspan="4" style="background:lightgrey" | 
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| colspan="4" align="center" | EDI
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|-
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| colspan="6" style="background:lightgrey" |
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| colspan="2" align="center" | DI
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|-
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| colspan="7" style="background:lightgrey" |
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| align="center" | DIL
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|}
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{| {{Prettytable}}
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! width="30pt" | 7
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! width="30pt" | 6
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! width="30pt" | 5
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! width="30pt" | 4
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! width="30pt" | 3
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! width="30pt" | 2
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! width="30pt" | 1
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! width="30pt" | 0
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|-
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| colspan="8" align="center" | RSI
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|-
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| colspan="4" style="background:lightgrey" | 
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| colspan="4" align="center" | ESI
 +
|-
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| colspan="6" style="background:lightgrey" |
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| colspan="2" align="center" | SI
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|-
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| colspan="7" style="background:lightgrey" |
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| align="center" | SIL
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|}
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 +
===Zeigerregister===
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{| {{Prettytable}}
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! width="30pt" | 7
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! width="30pt" | 6
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! width="30pt" | 5
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! width="30pt" | 4
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! width="30pt" | 3
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! width="30pt" | 2
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! width="30pt" | 1
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! width="30pt" | 0
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|-
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| colspan="8" align="center" | RBP
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|-
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| colspan="4" style="background:lightgrey" | 
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| colspan="4" align="center" | EBP
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|-
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| colspan="6" style="background:lightgrey" |
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| colspan="2" align="center" | BP
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|-
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| colspan="7" style="background:lightgrey" |
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| align="center" | BPL
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|}
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{| {{Prettytable}}
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! width="30pt" | 7
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! width="30pt" | 6
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! width="30pt" | 5
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! width="30pt" | 4
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! width="30pt" | 3
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! width="30pt" | 2
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! width="30pt" | 1
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! width="30pt" | 0
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|-
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| colspan="8" align="center" | RSP
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|-
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| colspan="4" style="background:lightgrey" | 
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| colspan="4" align="center" | ESP
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|-
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| colspan="6" style="background:lightgrey" |
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| colspan="2" align="center" | SP
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|-
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| colspan="7" style="background:lightgrey" |
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| align="center" | SPL
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|}
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{| {{Prettytable}}
 
{| {{Prettytable}}
 
! Bits  || Register
 
! Bits  || Register
Zeile 25: Zeile 389:
 
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|-
 
| 128 || XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15
 
| 128 || XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15
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|}
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{| {{Prettytable}}
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| 4
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| 2 || || 2
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| 1 || 1 || ||
 
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|}